Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA, the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another such FPGA, the Xilinx Virtex®-II FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. And yet another such FPGA is the Xilinx Virtex-II Pro™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “junction blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Signal propagation delay of a circuit under test may be tested by placing such a circuit under test within a ring oscillator, as described in additional detail in U.S. Pat. Nos. 6,452,459, 6,232,845, 6,219,305, 6,144,262, 6,075,418, and 5,790,479, collectively and singly referred to as the “Kingsley ring oscillator.” The Kingsley ring oscillator facilitates testing of signal propagation delay in part by being non-inverting. Thus, clock-to-out delay of a circuit under test may be tracked as a leading edge of an input signal tracks with a leading edge of a data output signal of the circuit under test.
However, this advantage has heretofore precluded testing propagation delay of shift registers. As is known, a rising-edge-triggered shift register having a 0101010101010101 data storage pattern may output a logic 1 responsive to a rising edge of an input clock signal, but on the next rising edge such output will be a logic 0. In other words, in this example, the next rising edge tracks to a falling edge of the output of the shift register.
Accordingly, it would be desirable and useful to provide means to test signal propagation delay of a shift register with edge polarity tracking from data input to data output.